| dc.contributor.author |
Patel, Rutu |
|
| dc.contributor.author |
Maheshwari, Om |
|
| dc.contributor.author |
Mohapatra, Nihar Ranjan |
|
| dc.contributor.other |
8th IEEE Electron Devices Technology and Manufacturing Conference (EDTM 2024) |
|
| dc.coverage.spatial |
India |
|
| dc.date.accessioned |
2024-05-16T14:32:40Z |
|
| dc.date.available |
2024-05-16T14:32:40Z |
|
| dc.date.issued |
2024-03-03 |
|
| dc.identifier.citation |
Patel, Rutu; Maheshwari, Om and Mohapatra, Nihar Ranjan, "Device design of step field plate RF LDMOS transistor for improved power amplifier applications", in the 8th IEEE Electron Devices Technology and Manufacturing Conference (EDTM 2024), Bangalore, IN, Mar. 03-06, 2024. |
|
| dc.identifier.uri |
https://doi.org/10.1109/EDTM58488.2024.10511850 |
|
| dc.identifier.uri |
https://repository.iitgn.ac.in/handle/123456789/10055 |
|
| dc.description.abstract |
This work discusses the optimization of a Step Field Plate (SFP) RF LDMOS transistor to enhance Power Amplifier (PA) performance. The impact of structural parameters: length of overlap between gate and P-well mask (Lw), between gate and N-LDD mask (Lx) and length of gate (LG) on transconductance, device capacitances and operating frequency of the transistor is analyzed. Next, they are fine tuned to maximize large signal performance- output power, gain, and efficiency- of a common source PA circuit. |
|
| dc.description.statementofresponsibility |
by Rutu Patel, Om Maheshwari and Nihar Ranjan Mohapatra |
|
| dc.language.iso |
en_US |
|
| dc.publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
|
| dc.subject |
LDMOS transistor |
|
| dc.subject |
Power amplifier |
|
| dc.subject |
RF |
|
| dc.title |
Device design of step field plate RF LDMOS transistor for improved power amplifier applications |
|
| dc.type |
Conference Paper |
|