Power-efficient approximate multipliers leveraging hybrid CMOS-memristor paradigm

Abstract

Approximate computing is an innovative paradigm that offers substantial advantages in power, area utilization, and speed. In various error-resilient tasks such as multimedia processing, image multiplication, and machine learning, approximate compressors and multipliers are widely employed. While approximate computing utilizing CMOS technology shows promise, there exists a potential for further efficiency gains through the integration of novel device technologies. Among these emerging technologies, memristors have demonstrated significant potential in enhancing circuit performance in terms of power consumption, delay, and area utilization. This study focuses on the design of hybrid CMOS-memristor circuits for approximate computing applications. Initially, we implement fundamental logic gates using the hybrid CMOS-memristor approach. Subsequently, we employ six distinct approximate 4–2 compressors, each with different accuracy-performance tradeoffs, and finally implement 4×4 multipliers using compressors. Results indicate that the hybrid CMOS-memristor logic outperforms conventional CMOS in terms of power and area efficiency, offering up to 88% reduction in power consumption and up to 50% reduction in transistor count. These findings highlight the interesting potential of the hybrid CMOS- memristor paradigm in boosting power and area efficiency for the development of approximate computing edge circuits and systems.