| dc.contributor.author |
Singh, Aishwarya |
|
| dc.contributor.author |
Maheshwari, Om |
|
| dc.contributor.author |
Mohapatra, Nihar Ranjan |
|
| dc.contributor.other |
8th IEEE Electron Devices Technology and Manufacturing Conference (EDTM 2024) |
|
| dc.coverage.spatial |
India |
|
| dc.date.accessioned |
2024-05-30T11:50:02Z |
|
| dc.date.available |
2024-05-30T11:50:02Z |
|
| dc.date.issued |
3/3/2024 |
|
| dc.identifier.citation |
Singh, Aishwarya; Maheshwari, Om and Mohapatra, Nihar Ranjan, "Dissecting parasitic capacitance in nanosheet FETs: an analytical perspective", in the 8th IEEE Electron Devices Technology and Manufacturing Conference (EDTM 2024), Bangalore, IN, Mar. 03-06, 2024. |
|
| dc.identifier.uri |
https://doi.org/10.1109/EDTM58488.2024.10512230 |
|
| dc.identifier.uri |
https://repository.iitgn.ac.in/handle/123456789/10107 |
|
| dc.description.abstract |
This work presents an approach to extract and analytically model the parasitic capacitance components in Nanosheet FETs. Along with parallel and fringing components, the junction capacitance which is a significant contributor to the total parasitic capacitance is accurately modeled for the first time. The fringing parasitic capacitance components are modeled using the Elliptical Integral Method. The model uses only one fitting parameter and is accurate across the device structural variations with only ~1.2% error. |
|
| dc.description.statementofresponsibility |
by Aishwarya Singh, Om Maheshwari and Nihar Ranjan Mohapatra |
|
| dc.language.iso |
en_US |
|
| dc.publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
|
| dc.subject |
Nanosheet FET |
|
| dc.subject |
Parasitic capacitance |
|
| dc.subject |
Elliptical integral method |
|
| dc.subject |
Junction capacitance |
|
| dc.title |
Dissecting parasitic capacitance in nanosheet FETs: an analytical perspective |
|
| dc.type |
Conference Paper |
|