dc.contributor.author |
Singh, Aishwarya |
|
dc.contributor.author |
Ganeriwala, Mohit D. |
|
dc.contributor.author |
Mohapatra, Nihar Ranjan |
|
dc.contributor.other |
8th IEEE Electron Devices Technology and Manufacturing Conference (EDTM 2024) |
|
dc.coverage.spatial |
India |
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dc.date.accessioned |
2024-05-30T11:50:02Z |
|
dc.date.available |
2024-05-30T11:50:02Z |
|
dc.date.issued |
3/3/2024 |
|
dc.identifier.citation |
Singh, Aishwarya; Ganeriwala, Mohit D. and Mohapatra, Nihar Ranjan, "Physics-based scalable compact model for terminal charge, intrinsic capacitance and drain current in nanosheet FETs", in the 8th IEEE Electron Devices Technology and Manufacturing Conference (EDTM 2024), Bangalore, IN, Mar. 03-06, 2024. |
|
dc.identifier.uri |
https://doi.org/10.1109/EDTM58488.2024.10511791 |
|
dc.identifier.uri |
https://repository.iitgn.ac.in/handle/123456789/10108 |
|
dc.description.abstract |
This work presents a physics-based SPICE compatible model for Nanosheet FETs, which provides explicit expressions for the drain current, terminal charges and intrinsic capacitances. The drain current model is based on the drift-diffusion formalism for carrier transport. The terminal charge and intrinsic capacitance models are calculated by adopting the Ward–Dutton linear charge partition scheme that guarantees charge conservation. The model uses the novel bottom-up approach to calculate the terminal charges, uses very few empirical parameters and is accurate across device dimensions and bias conditions. |
|
dc.description.statementofresponsibility |
by Aishwarya Singh, Mohit D. Ganeriwala and Nihar Ranjan Mohapatra |
|
dc.language.iso |
en_US |
|
dc.publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
|
dc.subject |
Terminal charges |
|
dc.subject |
Nanosheet FET |
|
dc.subject |
Ward-Dutton |
|
dc.subject |
Quantum confinement |
|
dc.subject |
Bottom-up scalable compact model |
|
dc.title |
Physics-based scalable compact model for terminal charge, intrinsic capacitance and drain current in nanosheet FETs |
|
dc.type |
Conference Paper |
|