Exploring sheet thickness scaling and substrate orientation for maximizing nanosheet pFET performance

Abstract

We explored the performance of p-type nanosheet FETs (NsFETs) with sheet thickness scaling using a well-calibrated subband BTE solver that accounts for quantum confinement. Our investigation revealed that despite enhancements in gate electrostatics, the confined pFETs exhibit significantly reduced hole mobility due to increased phonon and surface roughness scattering (SRS). It is also found that introducing uniaxial compressive stress into the channel with an ideally flat surface (very low surface roughness) could boost the pFET ON-current by approximately 2.5 times. Furthermore, by integrating p-type NsFETs on { 110 } substrate, rather than on conventional { 100 } substrate, it is likely to yield superior hole mobility and overall device performance, particularly at scaled sheet thicknesses.