Design and analysis of performance-efficient on-chip memories for error-Intolerant and error-resilient applications

dc.contributor.advisor	Mekie, Joycee
dc.contributor.author	Bharti, Pramod Kumar
dc.date.accessioned	2024-09-13T08:19:24Z
dc.date.available	2024-09-13T08:19:24Z
dc.date.issued	2023
dc.identifier.citation	Bharti, Pramod Kumar (2023). Design and analysis of performance-efficient on-chip memories for error-Intolerant and error-resilient applications. Gandhinagar: Indian Institute of Technology Gandhinagar, 174p. (Acc. No.: T01141).
dc.identifier.uri	https://repository.iitgn.ac.in/handle/123456789/10428
dc.description.statementofresponsibility	by Pramod Kumar Bharti
dc.format.extent	xxii, 174p.: hbk.; 30 cm
dc.language.iso	en_US
dc.publisher	Indian Institute of Technology Gandhinagar
dc.subject	System on Chip (SoC)
dc.subject	Static Random Access Memories (SRAMs)
dc.subject	Application Specific Integrated Circuits
dc.title	Design and analysis of performance-efficient on-chip memories for error-Intolerant and error-resilient applications
dc.type	Thesis
dc.contributor.department	Electrical Engineering
dc.description.degree	PhD