Dynamic resistance reduction methods for voltage clamp lowering to enhance GGNMOS ESD protection

Abstract

In a typical CMOS technology, Gate-Grounded NMOS (GGNMOS) configuration is often utilized for electrostatic discharge protection (ESD). All the CMOS technologies have a stringent requirement on the maximum voltage tolerance. However, inefficient ESD protection design can clamp the voltage beyond the maximum voltage of the circuit to be protected. This article discusses various GGNMOS design methodologies to reduce the clamping voltage in 180nm CMOS technology. The dynamic resistance (R dyn ) of GGNMOS which affects the clamping voltage during ESD strike and the leakage current during normal operation are simulated and compared for different layout designs (typical bulk, different body position, multi-finger, surrounded gate) via transmission line pulse (TLP) measurements. Comparing designs with fixed area, it is observed that the R dyn for multi-finger design is lowest whereas the enclosed gate design provides optimum R dyn and leakage current (5X smaller than the multi-finger design). This study allows us to improve performance (i.e. increasing ESD current capability) by lowering clamping voltage (lower than circuits maximum voltage) which is beneficial for any ESD design where Gate Grounded NMOS (GGNMOS) protection is preferred.