Training-free parameter extraction for compact device models using sequential Bayesian optimization with adaptive sampling

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dc.contributor.author Maheshwari, Om
dc.contributor.author Singh, Aishwarya
dc.contributor.author Mohapatra, Nihar Ranjan
dc.coverage.spatial United States of America
dc.date.accessioned 2024-11-08T10:39:02Z
dc.date.available 2024-11-08T10:39:02Z
dc.date.issued 2024-10
dc.identifier.citation Maheshwari, Om; Singh, Aishwarya and Mohapatra, Nihar Ranjan, "Training-free parameter extraction for compact device models using sequential Bayesian optimization with adaptive sampling", IEEE Transactions on Electron Devices, DOI: 10.1109/TED.2024.3478177, Oct. 2024.
dc.identifier.issn 0018-9383
dc.identifier.issn 1557-9646
dc.identifier.uri https://doi.org/10.1109/TED.2024.3478177
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/10737
dc.description.abstract This work presents a computationally efficient approach for extracting compact model parameters with minimal training requirements. Bayesian optimization (BO) is employed in multiple stages to predict the optimum compact model parameters. Initially, the methodology is applied to the MIT virtual source model (MVS 2.0) for extremely thin silicon-on-insulator (ETSOI) devices, nanosheet FETs (NsFETs), and MoS2 -based 2-D material-based FETs (2DFETs). Subsequently, it is demonstrated on the Berkeley short-channel IGFET model (BSIM) common multigate (CMG) compact model for NsFETs. Through sequential processing, adaptive sampling, successive domain reduction, and fine-tuned objective functions, the framework achieves precise and efficient fitting of both global and local model parameters across a range of devices, all in a reduced number of iterations, irrespective of the compact model used.
dc.description.statementofresponsibility by Om Maheshwari, Aishwarya Singh and Nihar Ranjan Mohapatra
dc.language.iso en_US
dc.publisher Institute of Electrical and Electronics Engineers (IEEE)
dc.subject 2-D material-based FET (2DFET)
dc.subject Bayesian optimization (BO)
dc.subject Berkeley short-channel IGFET model (BSIM) common multigate (CMG)
dc.subject Compact model
dc.subject Extremely thin silicon-on-insulator (ETSOI)
dc.subject MIT virtual source (MVS) model
dc.subject Nanosheet FET (NsFET)
dc.subject Parameter extraction
dc.title Training-free parameter extraction for compact device models using sequential Bayesian optimization with adaptive sampling
dc.type Article
dc.relation.journal IEEE Transactions on Electron Devices


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