dc.contributor.author |
Maheshwari, Om |
|
dc.contributor.author |
Singh, Aishwarya |
|
dc.contributor.author |
Mohapatra, Nihar Ranjan |
|
dc.coverage.spatial |
United States of America |
|
dc.date.accessioned |
2024-11-08T10:39:02Z |
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dc.date.available |
2024-11-08T10:39:02Z |
|
dc.date.issued |
2024-10 |
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dc.identifier.citation |
Maheshwari, Om; Singh, Aishwarya and Mohapatra, Nihar Ranjan, "Training-free parameter extraction for compact device models using sequential Bayesian optimization with adaptive sampling", IEEE Transactions on Electron Devices, DOI: 10.1109/TED.2024.3478177, Oct. 2024. |
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dc.identifier.issn |
0018-9383 |
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dc.identifier.issn |
1557-9646 |
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dc.identifier.uri |
https://doi.org/10.1109/TED.2024.3478177 |
|
dc.identifier.uri |
https://repository.iitgn.ac.in/handle/123456789/10737 |
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dc.description.abstract |
This work presents a computationally efficient approach for extracting compact model parameters with minimal training requirements. Bayesian optimization (BO) is employed in multiple stages to predict the optimum compact model parameters. Initially, the methodology is applied to the MIT virtual source model (MVS 2.0) for extremely thin silicon-on-insulator (ETSOI) devices, nanosheet FETs (NsFETs), and MoS2 -based 2-D material-based FETs (2DFETs). Subsequently, it is demonstrated on the Berkeley short-channel IGFET model (BSIM) common multigate (CMG) compact model for NsFETs. Through sequential processing, adaptive sampling, successive domain reduction, and fine-tuned objective functions, the framework achieves precise and efficient fitting of both global and local model parameters across a range of devices, all in a reduced number of iterations, irrespective of the compact model used. |
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dc.description.statementofresponsibility |
by Om Maheshwari, Aishwarya Singh and Nihar Ranjan Mohapatra |
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dc.language.iso |
en_US |
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dc.publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
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dc.subject |
2-D material-based FET (2DFET) |
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dc.subject |
Bayesian optimization (BO) |
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dc.subject |
Berkeley short-channel IGFET model (BSIM) common multigate (CMG) |
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dc.subject |
Compact model |
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dc.subject |
Extremely thin silicon-on-insulator (ETSOI) |
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dc.subject |
MIT virtual source (MVS) model |
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dc.subject |
Nanosheet FET (NsFET) |
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dc.subject |
Parameter extraction |
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dc.title |
Training-free parameter extraction for compact device models using sequential Bayesian optimization with adaptive sampling |
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dc.type |
Article |
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dc.relation.journal |
IEEE Transactions on Electron Devices |
|