Robust and high-performance digital in-memory computing in 5T gain cell embedded DRAM

Abstract

This paper proposes a novel 5T Dual Port Gain Cell (5T-DPGC) embedded DRAM design for digital in-memory computing (IMC). The proposed 5T-DPGC-eDRAM cell enables the execution of N-input logical operations (specifically NAND/NOR) within the IMC without requiring any additional peripherals. Further, it allows for MAC operations using an extra compute circuit. The circuit implementation was carried out using CMOS 28 nm technology. The proposed cell gives an area benefit of 25% compared to standard 6T-SRAM. To evaluate the performance, we performed a post-layout simulation of 16 kB (128 × 128) 5T-DPGC-eDRAM array, and it achieves a throughput of 224 GOPS. Moreover, it demonstrated an energy efficiency of 8.21 TOPS/W at 0.65 V and 0.25 GHz, which is 1.61 × better than the SOTA 6T-SRAM-based digital IMC for 8-bit addition. Additionally, our design achieved a frequency of 1.75 GHz at 0.9 V. In terms of area efficiency, our approach reached 1.98 TOPS/mm2, surpassing the SOTA 6T-SRAM-based digital IMC by 1.33 ×.