dc.contributor.author |
Pokharia, Monika |
|
dc.contributor.author |
Trivedi, Het |
|
dc.contributor.author |
Doshi, Siddharth |
|
dc.contributor.author |
Hegde, Ravi S. |
|
dc.contributor.author |
Mekie, Joycee |
|
dc.coverage.spatial |
India |
|
dc.date.accessioned |
2025-03-06T09:37:55Z |
|
dc.date.available |
2025-03-06T09:37:55Z |
|
dc.date.issued |
2025-01-04 |
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dc.identifier.citation |
Pokharia, Monika; Trivedi, Het; Doshi, Siddharth; Hegde, Ravi S. and Mekie, Joycee, "HyCMAx: power-efficient hybrid CMOS-memristor based approximate dividers for error-resilient applications", in the 38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID 2025), Bangalore, IN, Jan. 04-08, 2025. |
|
dc.identifier.uri |
https://doi.org/10.1109/VLSID64188.2025.00092 |
|
dc.identifier.uri |
https://repository.iitgn.ac.in/handle/123456789/11092 |
|
dc.description.abstract |
Approximate computing is a promising paradigm for improving the performance parameters of electronic systems at the expense of accuracy in error-resilient tasks such as multimedia processing, image multiplication, and neural networks. While approximate circuits utilizing CMOS technology have been extensively studied, integrating approximate computing with emerging technologies like memristors offers further performance enhancements. HyCMAx investigates a hybrid CMOS-memristor approach for designing approximate circuits. In this paper, an approximate subtractor has been proposed, which was subsequently used to implement a restoring divider using the hybrid CMOS-memristor approach. HyCMAx dividers implemented in 28nm CMOS technology node gave up to ~43.8% dynamic power reduction and ~31.3% transistor count reduction as compared to only-CMOS implementation. Different levels of approximation were introduced in the divider to study the limits of approximation, which would give acceptable results. The proposed designs were then evaluated in the context of neural networks and image processing applications. This study highlights the potential of combining CMOS and memristor technologies to create high-performance, power-efficient approximate circuits suitable for various error-resilient computational tasks. |
|
dc.description.statementofresponsibility |
by Monika Pokharia, Het Trivedi, Siddharth Doshi, Ravi S. Hegde and Joycee Mekie |
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dc.language.iso |
en_US |
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dc.subject |
Hybrid-CMOS memristor |
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dc.subject |
Approximate subtractor |
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dc.subject |
Restoring divider |
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dc.subject |
Image processing |
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dc.subject |
Neural networks |
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dc.title |
HyCMAx: power-efficient hybrid CMOS-memristor based approximate dividers for error-resilient applications |
|
dc.type |
Conference Paper |
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dc.relation.journal |
38th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID 2025) |
|