A low leakage variations and high stability 9T SRAM cells

Abstract

This paper introduces an alternative NLP-9T/PLP-9T SRAM cell designs that demonstrates improved stability and low leakage power variations at worst case analysis. The suggested SRAM cells mitigate read disturbances by deactivating the access transistors within the memory cell. Moreover, the inclusion of extra PMOS read access transistors along the bitlines helps to ensure a successful read operation. The results indicate that the suggested PLP-9T memory cell exhibit stability that is 1.31 times greater than 6T-SRAM, 1.05 times higher than CONV-8T, 1.27 times higher than WU-Z8T, 1.25 times higher than LIU-D1oT, and 1.022 times higher than the proposed NLP-9T memory cells. Furthermore, the proposed cells in standby mode effectively limits leakage power, even under the most adverse process fluctuations. However, the suggested NLP-9T/PLP-9T design takes about 1.7 times/1.3 times more layout area than the traditional 6T -SRAM.