Effect of Device Geometries on HCI and PBTI of Gate First High-K Metal Gate NMOS Transistors

Abstract

As the scaling of MOS transistor is approaching the physical limits, large leakage current is becoming a major obstacle. Therefore, high-K materials have been introduced as gate dielectrics in the transistors to further continue technology miniaturization. However, reliability of MOS transistors with high- K/Metal gate structure has become a serious concern, because of more defects in gate dielectric, and introduction of capping layers (La for NMOS and Al for PMOS). Hot carrier injection (HCI) and bias temperature instability (BTI) still remain the key reliability issues. In recent technology nodes, the Positive BTI (PBTI) component cannot be avoided in HCI stress, and this seriously affects the accurate life time prediction of the device. This work aims at decoupling of the PBTI component from HCI stress using their distinct behaviour at elevated temperature. A unique trend of HCI degradation with the variation in the device width has been shown where wider devices are more prone to degradation. It can be due to more number of nonuniformly distributed oxygen vacancies present in the wider devices. It has also been observed that increase in capping layer (La) thickness in the NMOS transistor increases the total degradation and we have attributed this to the stress induced trap generation in the bulk oxide.