| dc.contributor.author |
Mohapatra, Nihar Ranjan |
|
| dc.contributor.author |
Naresh, Satya Siva |
|
| dc.contributor.author |
Duhan, Pardeep |
|
| dc.contributor.other |
2015 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) |
|
| dc.coverage.spatial |
TW |
|
| dc.date.accessioned |
2015-06-26T10:50:17Z |
|
| dc.date.available |
2015-06-26T10:50:17Z |
|
| dc.date.issued |
2015-04 |
|
| dc.identifier.citation |
Mohapatra, Nihar R.; Naresh, Satya Siva and Duhan, Pardeep,"Analog performance of gate-first HKMG NMOS transistors - Role of device dimensions and layout", in the 2015 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), Ambassador Hotel, Hsinchu, TW, Apr. 27-29, 2015. |
en_US |
| dc.identifier.uri |
https://repository.iitgn.ac.in/handle/123456789/1792 |
|
| dc.description.abstract |
In this paper, we analyze the role of device dimensions and layout/design rules on the analog performance of HKMG NMOS transistors. We have shown ∼28% improvement in the intrinsic gain and ∼26% improvement in the gm/Id for an 80nm wide transistor compared to a 1μm wide one. We have also shown that the analog performance of transistors could be improved further by dividing a single active into multiple active fingers, by increasing the active to active spacing and by eliminating the active dummies. |
en_US |
| dc.description.statementofresponsibility |
by Nihar R. Mohapatra, Satya Siva Naresh and Pardeep Duhan |
|
| dc.language.iso |
en |
en_US |
| dc.publisher |
IEEE |
en_US |
| dc.subject |
CMOS integrated circuits |
en_US |
| dc.subject |
Fingers |
en_US |
| dc.subject |
Layout |
en_US |
| dc.subject |
Logic gates |
en_US |
| dc.subject |
MOSFET |
en_US |
| dc.subject |
Performance evaluation |
en_US |
| dc.title |
Analog performance of gate-first HKMG NMOS transistors - Role of device dimensions and layout |
en_US |
| dc.type |
Article |
en_US |