Study of Variability and Technology Scaling on Synchronizers and Design of Metastable-hard Synchronizers

Abstract

Synchronizers are used at the clock domain crossings and at asynchronous interfaces to reduce the probability of failure due to metastability. Metastability parameter plays a key role in deciding the synchronizer performance. The existing work on synchronizers has focused on understanding this parameter and its dependence on variations and technology scaling. The standard cell library flip-flops used as synchronizers are not really optimized for synchronization. In this work, the properties of conventional flip-flops and synchronizers are studied and a semi-automated approach to optimize a standard cell library flip-flop for synchronization is presented. The resulting synchronizer shows 5 improvement in MTBF compared to the conventional design. Area and propagation delay improvement is also obtained. Exhaustive simulations at different technology nodes (180nm, 130nm, 90nm and 65nm) are done in Cadence Spectre to validate the analytical results. Opposite trends are observed between simulations and measurements, but the reasons for these observations are not well-understood. In this work, this gap has been filled through detailed study and analysis of the effects of technology scaling on . It is shown through this work that process parameters fluctuations has significant impact on , and due to these variations, one may observe devolution or scaling of as technology scales. We find that among the several process parameters, mobility and threshold voltage significantly affect. The effect of large variations in these parameters is that one cannot exactly predict the trend in as technology scales. In this study, analysis of three different designs are done to confirm the findings. Further, the difference in between the master and slave latches have been studied.