Interfaces for ratiochronous network on chips

Abstract

Network on Chip is the most promising on chip interconnect solution for large multicore systems. Synchronized clocking is a major problem in large multicore systems. The growing number of systems consist of large networks with hetero geneous cores. The performance of such large systems is largely dependant on the frequency of the slowest running core as it decides the entire system frequency. The performance would be at its best if the cores were to run at their independent best frequencies. We need an interconnect fabric which best matches these de mands. Hence in this thesis we propose, prove, implement and test interfaces for the existing NoC fabric that will allow communication between the cores being clocked at rational set of frequencies.The interface is implemented and tested on FPGA and an ASIC is fabricated using umc 65nm technology. This interface will allow set of cores to operate at their individual best frequency and thus not limit the performance of entire chip by the slowest running core. Exact performance gains will be dictated by the core utilization pattern and the range of frequencies being targetted in the multicore system.