Role of device dimensions and layout on the analog performance of gate-first HKMG nMOS transistors

Abstract

This paper discusses in detail the effects of device dimensions and layout/design rules on the analog performance of gate-first high-K gate dielectrics and metal gate (HKMG) nMOS transistors. It is observed through detailed measurements that the transconductance of HKMG nMOS transistors increases with the reduction in the channel width. The 80-nm wide HKMG nMOS transistors show 1.3× improvement in the intrinsic gain and ~27% improvement in the transconductance generation efficiency compared with a 1000-nm wide transistor. The similar behavior is observed for all gate lengths. The physical mechanisms responsible for this behavior are identified and explained. It is finally shown that the analog performance of the HKMG nMOS transistors could be further improved by dividing a single active finger into multiple active fingers, by increasing active-to-active spacing, by increasing the gate pitch, and by eliminating the active dummies.