Abstract:
This paper shows the circuit level performance comparison of low-? and high-? spacer Junctionless FinFET(J-FinFET). TCAD simulations show that for high-? (HfO2, ?=22) spacer J-FinFET, the device performance parameters such as DIBL (drain induced barrier lowering), SS (sub-threshold swing) and ION/IOFF improved by 14.5 %, 5% and 3.5x respectively as compared to low-? (SiO2, ?=3.9) spacer J-FinFET. Interestingly, the same is not true for the circuit-level parameters. Results of circuit-level performances show that for high-? spacer J-FinFET circuits, delay and power consumption is increased by minimum 40% and 36%, respectively, as compared to their corresponding low-? spacer J-FinFET circuits. Our analysis shows that performance degradation in high-? spacer J-FinFET is due to increased fringe capacitance in high-? spacer J-FinFET.