Computationally efficient analytic charge model for III-V cylindrical nanowire transistors

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dc.contributor.author Ganeriwala, Mohit D.
dc.contributor.author Marin, Enrique G.
dc.contributor.author Ruiz, Francisco G.
dc.contributor.author Mohapatra, Nihar Ranjan
dc.contributor.other 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS),
dc.coverage.spatial Granada,ES
dc.date.accessioned 2018-08-23T05:49:53Z
dc.date.available 2018-08-23T05:49:53Z
dc.date.issued 2018-03-19
dc.identifier.citation Ganeriwala, Mohit D.; Marin, Enrique G.; Ruiz, Francisco G. and Mohapatra, Nihar R., "Computationally efficient analytic charge model for III-V cylindrical nanowire transistors", in the 2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), Granada, ES, Mar. 19-21, 2018. en_US
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/3877
dc.description.statementofresponsibility by Mohit. D. Ganeriwala, Enrique G. Marin, Francisco G. Ruiz and Nihar R.Mohapatra
dc.language.iso en en_US
dc.title Computationally efficient analytic charge model for III-V cylindrical nanowire transistors en_US
dc.type Article en_US


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