| dc.contributor.author |
Sarath Chandran, G. M. |
|
| dc.contributor.author |
Ganeriwala, Mohit D. |
|
| dc.contributor.author |
Mohapatra, Nihar Ranjan |
|
| dc.contributor.other |
2nd International Symposium on Devices, Circuits and Systems (ISDCS 2019) |
|
| dc.coverage.spatial |
Higashi-Hiroshima, JP |
|
| dc.date.accessioned |
2019-06-29T06:04:57Z |
|
| dc.date.available |
2019-06-29T06:04:57Z |
|
| dc.date.issued |
2019-03 |
|
| dc.identifier.citation |
Sarath Chandran, G. M.; Ganeriwala, Mohit D. and Mohapatra, Nihar Ranjan, "Capacitance and surface potential model for III-V double-gate FET", in the 2nd International Symposium on Devices, Circuits and Systems (ISDCS 2019), Higashi-Hiroshima, JP, Mar. 6-8, 2019. |
en_US |
| dc.identifier.uri |
https://repository.iitgn.ac.in/handle/123456789/4586 |
|
| dc.description.statementofresponsibility |
by G.M. Sarath Chandran, Mohit D. Ganeriwala and Nihar Ranjan Mohapatra |
|
| dc.language.iso |
en |
en_US |
| dc.title |
Capacitance and surface potential model for III-V double-gate FET |
en_US |
| dc.type |
Article |
en_US |