Effect of sub-10nm fin-widths on the analog performance of FinFETs

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dc.contributor.author Bhoir, Mandar S.
dc.contributor.author Mohapatra, Nihar Ranjan
dc.contributor.author Chiarella, Thomas
dc.contributor.author Ragnarsson, Lars �ke
dc.contributor.author Mitard, Jerome
dc.contributor.author Terzeiva, Valentina
dc.contributor.author Horiguchi, Naoto
dc.contributor.other 2019 Electron Devices Technology and Manufacturing Conference (EDTM 2019)
dc.coverage.spatial Singapore, SG
dc.date.accessioned 2019-07-16T09:58:27Z
dc.date.available 2019-07-16T09:58:27Z
dc.date.issued 2019-03-12
dc.identifier.citation Bhoir, Mandar S.; Mohapatra, Nihar R.; Chiarella, Thomas; Ragnarsson, Lars �ke; Mitard, Jerome; Terzeiva, Valentina and Horiguchi, Naoto, �Effect of sub-10nm fin-widths on the analog performance of FinFETs�, in the 2019 Electron Devices Technology and Manufacturing Conference (EDTM 2019), Singapore, SG, Mar. 12-15, 2019. en_US
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/4614
dc.description.statementofresponsibility by Mandar S. Bhoir, Nihar R. Mohapatra, Thomas Chiarella, Lars �ke Ragnarsson, Jerome Mitard, Valentina Terzeiva and Naoto Horiguchi
dc.language.iso en en_US
dc.title Effect of sub-10nm fin-widths on the analog performance of FinFETs en_US
dc.type Article en_US


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