Charge and capacitance modeling of III-V double gate field effect transistors

dc.contributor.advisor	Mohapatra, Nihar Ranjan
dc.contributor.author	Chandran, Sarath G.M.
dc.date.accessioned	2019-08-29T09:48:14Z
dc.date.available	2019-08-29T09:48:14Z
dc.date.issued	2019
dc.identifier.citation	Chandran, Sarath G.M. (2019). Charge and capacitance modeling of III-V double gate field effect transistors. Gandhinagar: Indian Institute of Technology Gandhinagar, 60p. (Acc. No.: T00465).
dc.identifier.uri	https://repository.iitgn.ac.in/handle/123456789/4744
dc.description.statementofresponsibility	by Sarath G.M. Chandran
dc.format.extent	ix, 60p.: ill.; 30 cm.
dc.language.iso	en_US
dc.publisher	Indian Institute of Technology Gandhinagar
dc.subject	17210092
dc.subject	Electrical Engineering
dc.subject	Moore's Law
dc.subject	IG-DGFET
dc.subject	Multi-gate FET
dc.subject	Short Channel Effects
dc.subject	Fermi-Dirac Statistics
dc.title	Charge and capacitance modeling of III-V double gate field effect transistors
dc.type	Thesis
dc.contributor.department	Electrical Engineering
dc.description.degree	M.Tech.