Design of novel CMOS based inexact subtractors and dividers for approximate computing: an in-depth comparison with PTL based designs

Abstract

Multimedia applications consume an immense amount of energy. These applications have division as one of the fundamental operations. Division is also one of the costliest operations in terms of energy consumption. Thus, various works have been done to address the issue of energy consumption in multimedia applications by using approximate dividers based on pass transistor logic (PTL). Since these applications have resilience towards erroneous computations huge energy benefits are obtained as a result of approximate computations with similar output quality. In this paper, we have shown that PTL based designs are not suitable for lower technology nodes. We performed an in-depth analysis using UMC 65nm and UMC 28nm to highlight the adverse effects of technology scaling on energy consumption and delay in PTL based design as compared to CMOS based designs. We also propose four different inexact CMOS subtractor (ICS) designs, as they are the basic repeated module in inexact restoring array dividers (IRADs). Our proposed ICS designs consume ~ 2� lesser dynamic energy, ~ 3� lesser static power and have ~ 2.5� lesser delay as compared to the existing PTL based designs in UMC 65nm. These benefits increase for UMC 28nm, which shows PTL based designs further worsens at lower technology nodes. IRADs also give about 50% reduction in energy consumption with only 3% degradation in Structural Similarity (SSIM) Index, an image quality metric in multimedia applications like change detection, background removal, and JPEG compression, as compared to exact restoring array divider (ERAD).