| dc.contributor.author |
Ganeriwala, Mohit D |
|
| dc.contributor.author |
Marin,Enrique G. |
|
| dc.contributor.author |
Ruiz, Francisco G. |
|
| dc.contributor.author |
Mohapatra, Nihar R. |
|
| dc.contributor.other |
2020 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India) |
|
| dc.coverage.spatial |
Hyderabad, IN |
|
| dc.date.accessioned |
2020-02-22T06:10:44Z |
|
| dc.date.available |
2020-02-22T06:10:44Z |
|
| dc.date.issued |
2019-02-25 |
|
| dc.identifier.citation |
Ganeriwala, Mohit D; Marin,Enrique G.; Ruiz, Francisco G. and Mohapatra, Nihar R., "Charge and capacitance compact model for III-V quadruple-gate FETs with square geometry", in the 2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India), Hyderabad, IN, Feb. 25-27, 2019. |
en_US |
| dc.identifier.uri |
https://repository.iitgn.ac.in/handle/123456789/5094 |
|
| dc.description.statementofresponsibility |
by Mohit D Ganeriwala, Enrique G. Marin, Francisco G. Ruiz and Nihar R. Mohapatra |
|
| dc.language.iso |
en_US |
en_US |
| dc.title |
Charge and capacitance compact model for III-V quadruple-gate FETs with square geometry |
en_US |
| dc.type |
Article |
en_US |