| dc.contributor.author |
Devnath, Joydeep Kumar |
|
| dc.contributor.author |
Surana, Neelam |
|
| dc.contributor.author |
Mekie, Joycee |
|
| dc.contributor.other |
2020 IEEE International Symposium on Circuits and Systems (ISCAS) |
|
| dc.coverage.spatial |
Sevilla, ES |
|
| dc.date.accessioned |
2020-10-09T09:55:57Z |
|
| dc.date.available |
2020-10-09T09:55:57Z |
|
| dc.date.issued |
2020-10-12 |
|
| dc.identifier.citation |
Devnath, Joydeep Kumar; Surana, Neelam and Mekie, Joycee, "A low-voltage split memory architecture for binary neural networks", in the 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, ES, Oct. 12-14, 2020. |
en_US |
| dc.identifier.uri |
https://repository.iitgn.ac.in/handle/123456789/5765 |
|
| dc.description.statementofresponsibility |
by Joydeep Kumar Devnath, Neelam Surana and Joycee Mekie |
|
| dc.language.iso |
en_US |
en_US |
| dc.title |
A low-voltage split memory architecture for binary neural networks |
en_US |
| dc.type |
Conference Papers |
en_US |