| dc.contributor.author |
Jha, Chandan Kumar |
|
| dc.contributor.author |
Prasad, Kailash |
|
| dc.contributor.author |
Tomar, Arun Singh |
|
| dc.contributor.author |
Mekie, Joycee |
|
| dc.contributor.other |
2020 IEEE International Symposium on Circuits and Systems (ISCAS) |
|
| dc.coverage.spatial |
Sevilla, ES |
|
| dc.date.accessioned |
2020-10-09T09:55:57Z |
|
| dc.date.available |
2020-10-09T09:55:57Z |
|
| dc.date.issued |
2020-10-12 |
|
| dc.identifier.citation |
Jha, Chandan Kumar; Prasad, Kailash; Tomar, Arun Singh and Mekie, Joycee, "SEDAAF: FPGA based single exact dual approximate adders for approximate processors", in the 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, ES, Oct. 12-14, 2020. |
en_US |
| dc.identifier.uri |
https://repository.iitgn.ac.in/handle/123456789/5767 |
|
| dc.description.statementofresponsibility |
by Chandan Kumar Jha, Kailash Prasad, Arun Singh Tomar, and Joycee Mekie |
|
| dc.language.iso |
en_US |
en_US |
| dc.title |
SEDAAF: FPGA based single exact dual approximate adders for approximate processors |
en_US |
| dc.type |
Conference Papers |
en_US |