Vt extraction methodologies influence process induced Vt variability: does this fact still hold for advanced technology nodes?

Abstract

In this work, we have investigated the influence of ${V}_{\text {t}}$ extraction procedure on overall ${V}_{\text {t}}$ variability of sub-10 nm ${W}_{\text {fin}}$ FinFETs. Using six different ${V}_{\text {t}}$ extraction techniques, we have experimentally demonstrated that the ${V}_{\text {t}}$ variability is independent of ${V}_{\text {t}}$ extraction procedure (unlike reported earlier). Furthermore, through systematic evaluation on commonly used ${V}_{\text {t}}$ extraction techniques, the physics behind this anomalous behavior is investigated. It is shown that the significant variation in metal gate work-function and gate dielectric charges in advanced CMOS nodes is mainly responsible for this behavior. This claim is further validated for FinFETs with deeply scaled fin-width and effective oxide thickness (EOT).