Compact electrostatics and transport model for high mobility iii-v channel gate-all-around MOS transistors

dc.contributor.advisor	Mohapatra, Nihar Ranjan
dc.contributor.author	Ganeriwala, Mohit D.
dc.date.accessioned	2020-12-03T09:25:55Z
dc.date.available	2020-12-03T09:25:55Z
dc.date.issued	2020
dc.identifier.citation	Ganeriwala, Mohit D. (2020). Compact electrostatics and transport model for high mobility iii-v channel gate-all-around MOS transistors. Gandhinagar: Indian Institute of Technology Gandhinagar, 123p. (Acc. No.: T00527).
dc.identifier.uri	https://repository.iitgn.ac.in/handle/123456789/5933
dc.description.statementofresponsibility	by Mohit D. Ganeriwala
dc.format.extent	xxii, 123p.: ill.; 30 cm.
dc.language.iso	en_US
dc.publisher	Indian Institute of Technology Gandhinagar
dc.subject	13210026
dc.subject	Electrical Engineering
dc.subject	Semiconductor Materials
dc.subject	MOS Transistors
dc.subject	Circuit Simulators
dc.subject	Cross-sectional Geometries
dc.title	Compact electrostatics and transport model for high mobility iii-v channel gate-all-around MOS transistors
dc.type	Thesis
dc.contributor.department	Electrical Engineering
dc.description.degree	Ph.D.