ASOCC: an evaluation framework for asynchronous and synchronous network-on-chip architectures

dc.contributor.advisor	Mekie, Joycee
dc.contributor.author	Sneha
dc.date.accessioned	2020-12-03T09:25:56Z
dc.date.available	2020-12-03T09:25:56Z
dc.date.issued	2020
dc.identifier.citation	Sneha (2020). ASOCC: an evaluation framework for asynchronous and synchronous network-on-chip architectures. Gandhinagar: Indian Institute of Technology Gandhinagar, 191p. (Acc. No.: T00535).
dc.identifier.uri	https://repository.iitgn.ac.in/handle/123456789/5941
dc.description.statementofresponsibility	by Sneha
dc.format.extent	xii, 191p.: ill.; 30 cm.
dc.language.iso	en_US
dc.publisher	Indian Institute of Technology Gandhinagar
dc.subject	13310023
dc.subject	Electrical Engineering
dc.subject	Synchronous Systems
dc.subject	Network-on-chip
dc.subject	PANE Models
dc.subject	Routing Algorithms
dc.subject	Router Architectures
dc.title	ASOCC: an evaluation framework for asynchronous and synchronous network-on-chip architectures
dc.type	Thesis
dc.contributor.department	Electrical Engineering
dc.description.degree	Ph.D.