Design of memory compiler for embedded memories

dc.contributor.advisor	Mekie, Joycee
dc.contributor.author	Tiwari, Gyanendra K
dc.date.accessioned	2020-12-03T09:26:01Z
dc.date.available	2020-12-03T09:26:01Z
dc.date.issued	2020
dc.identifier.citation	Tiwari, Gyanendra K. (2020). Design of memory compiler for embedded memories. Gandhinagar: Indian Institute of Technology Gandhinagar, 84p. (Acc. No.: T00649).
dc.identifier.uri	https://repository.iitgn.ac.in/handle/123456789/6055
dc.description.statementofresponsibility	by Gyanendra K. Tiwari
dc.format.extent	xii, 84p.: ill.; 30 cm.
dc.language.iso	en_US
dc.publisher	Indian Institute of Technology Gandhinagar
dc.subject	18210101
dc.subject	Electrical Engineering
dc.subject	System On Chips
dc.subject	Memory Compiler Flow
dc.subject	Memory Cells
dc.subject	SRAM Cell
dc.title	Design of memory compiler for embedded memories
dc.type	Thesis
dc.contributor.department	Electrical Engineering
dc.description.degree	M.Tech.