Framework for synchronous to asynchronous design conversion

dc.contributor.advisor	Mekie, Joycee
dc.contributor.author	Sah, Jitesh
dc.date.accessioned	2020-12-03T09:26:01Z
dc.date.available	2020-12-03T09:26:01Z
dc.date.issued	2020
dc.identifier.citation	Sah, Jitesh (2020). Framework for synchronous to asynchronous design conversion. Gandhinagar: Indian Institute of Technology Gandhinagar, 98p. (Acc. No.: T00650).
dc.identifier.uri	https://repository.iitgn.ac.in/handle/123456789/6056
dc.description.statementofresponsibility	by Jitesh Sah
dc.format.extent	xiv, 98p.: ill.; 30 cm.
dc.language.iso	en_US
dc.publisher	Indian Institute of Technology Gandhinagar
dc.subject	18210103
dc.subject	Electrical Engineering
dc.subject	Low Power Synchronous Domain
dc.subject	Radiation Hardened Synchronous
dc.subject	Asynchronous Techniques
dc.subject	Glitch Filtering
dc.title	Framework for synchronous to asynchronous design conversion
dc.type	Thesis
dc.contributor.department	Electrical Engineering
dc.description.degree	M.Tech.