Development and validation of compact models for LDMOS transistor with channel doping gradient

dc.contributor.advisor	Mohapatra, Nihar Ranjan
dc.contributor.author	Patil, Shubham
dc.date.accessioned	2020-12-03T09:26:01Z
dc.date.available	2020-12-03T09:26:01Z
dc.date.issued	2020
dc.identifier.citation	Patil, Shubham (2020). Development and validation of compact models for LDMOS transistor with channel doping gradient. Gandhinagar: Indian Institute of Technology Gandhinagar, 90p. (Acc. No.: T00653).
dc.identifier.uri	https://repository.iitgn.ac.in/handle/123456789/6059
dc.description.statementofresponsibility	by Shubham Patil
dc.format.extent	xv, 90p.: ill.; 30 cm.
dc.language.iso	en_US
dc.publisher	Indian Institute of Technology Gandhinagar
dc.subject	18210112
dc.subject	Electrical Engineering
dc.subject	High Voltage Devices
dc.subject	Power Management Integrated Circuits
dc.subject	HiSIM-HV2 Model
dc.subject	Circuit Simulator
dc.subject	Gate Charge
dc.title	Development and validation of compact models for LDMOS transistor with channel doping gradient
dc.type	Thesis
dc.contributor.department	Electrical Engineering
dc.description.degree	M.Tech.