A novel ML augmented DRC framework for identification of yield detractor patterns

Abstract

This work proposes a methodology to find lithography yield detractors using Design Rule Checks (DRC) that are derived from a supervised Machine Learning (ML) model. The probability of being an outlier in layout parameter domain has a strong correlation with the probability of process failure. Moreover, the failing patterns exhibit relatively complex and non-linear behavior and often form complex clusters in the layout parameter domain. Using this, an accurate failure model is built by measuring the distance of a layout sample from the mean distribution in the layout parameter space. The proposed method does not require process failure models, but the calculation of layout parameters only. Further, the failure models are converted into DRC rules to make the methodology suitable for integration into present verification flow. These ML augmented Design Rule Checks (MLDRC) use a set of decision trees in the layout parameter domain and are suitable for full-chip level applications. The ML augmented DRC can better represent and form failure clusters as compared to traditional DRC. Experimental results show that the proposed MLDRC achieves better performance on full-chip designs compared to other hotspot detection techniques.