| dc.contributor.author |
Ganeriwala, Mohit D. |
|
| dc.contributor.author |
Ruiz, Francisco G. |
|
| dc.contributor.author |
Marin, Enrique G. |
|
| dc.contributor.author |
Mohapatra, Nihar Ranjan |
|
| dc.coverage.spatial |
United Kingdom |
|
| dc.date.accessioned |
2012-09-19T16:39:14Z |
|
| dc.date.available |
2012-09-19T16:39:14Z |
|
| dc.date.issued |
2021-08 |
|
| dc.identifier.citation |
Ganeriwala, Mohit D.; Ruiz, Francisco G.; Marin, Enrique G. and Mohapatra, Nihar Ranjan, "A unified compact model for electrostatics of III-V GAA transistors with different geometries", Journal of Computational Electronics, DOI: 10.1007/s10825-021-01751-2, Aug. 2021. |
en_US |
| dc.identifier.issn |
1569-8025 |
|
| dc.identifier.issn |
1572-8137 |
|
| dc.identifier.uri |
https://doi.org/10.1007/s10825-021-01751-2 |
|
| dc.identifier.uri |
https://repository.iitgn.ac.in/handle/123456789/6803 |
|
| dc.description.abstract |
"In this work, a physics-based unifed compact model for III-V GAA FET electrostatics is proposed. The model consid ers arbitrary cross-sectional geometry of GAA FETs viz. rectangular, circular and elliptical. A comprehensive model for cuboid GAA FETs is developed frst using the constant charge density approximation. The model is then combined with the earlier developed model for cylindrical GAA FETs to have a unifed representation. The efcacy of the model is validated by comparing it with simulation data from a 2D coupled Poisson-Schrodinger solver. The proposed model is found to be, (a) accurate for GAA FETs with diferent geometries, dimensions and channel materials and (b) computationally efcient" |
|
| dc.description.statementofresponsibility |
by Mohit D. Ganeriwala, Francisco G. Ruiz, Enrique G. Marin and Nihar R. Mohapatra |
|
| dc.language.iso |
en_US |
en_US |
| dc.publisher |
Springer |
en_US |
| dc.subject |
Gate all around FET |
en_US |
| dc.subject |
Nanowire |
en_US |
| dc.subject |
III-V |
en_US |
| dc.subject |
Compact model |
en_US |
| dc.subject |
Charge |
en_US |
| dc.subject |
Surface potential |
en_US |
| dc.subject |
Capacitance |
en_US |
| dc.subject |
Circuit simulation |
en_US |
| dc.title |
A unified compact model for electrostatics of III-V GAA transistors with different geometries |
en_US |
| dc.type |
Article |
en_US |
| dc.relation.journal |
Journal of Computational Electronics |
|