Compact model of LDMOS transistors at low temperature

dc.contributor.advisor	Mohapatra, Nihar Ranjan
dc.contributor.author	Kuldip, Shah Mansi
dc.date.accessioned	2021-10-27T14:12:41Z
dc.date.available	2021-10-27T14:12:41Z
dc.date.issued	2021
dc.identifier.citation	Kuldip, Shah Mansi (2021). Compact model of LDMOS transistors at low temperature. Gandhinagar: Indian Institute of Technology Gandhinagar, 69p. (Acc. No.: T00867).
dc.identifier.uri	https://repository.iitgn.ac.in/handle/123456789/7158
dc.description.statementofresponsibility	by Shah Mansi Kuldip
dc.format.extent	xi, 69p.: ill.; hbk.; 30 cm.
dc.language.iso	en_US
dc.publisher	Indian Institute of Technology Gandhinagar
dc.subject	19210084
dc.subject	Cryogenics
dc.subject	Applied Physics
dc.subject	Silicon Transistors
dc.subject	Mosfet circuits
dc.subject	Computer Aided Design
dc.title	Compact model of LDMOS transistors at low temperature
dc.type	Thesis
dc.contributor.department	Electrical Engineering
dc.description.degree	M.Tech