| dc.contributor.author |
Ganeriwala, Mohit D. |
|
| dc.contributor.author |
Singh, Aishwarya |
|
| dc.contributor.author |
Dubey, Abhilash |
|
| dc.contributor.author |
Kaur, Ramandeep |
|
| dc.contributor.author |
Mohapatra, Nihar Ranjan |
|
| dc.coverage.spatial |
United States of America |
|
| dc.date.accessioned |
2021-12-24T11:50:54Z |
|
| dc.date.available |
2021-12-24T11:50:54Z |
|
| dc.date.issued |
2022-01 |
|
| dc.identifier.citation |
Ganeriwala, Mohit D.; Singh, Aishwarya; Dubey, Abhilash; Kaur, Ramandeep and Mohapatra, Nihar Ranjan, “A bottom-up scalable compact model for quantum confined nanosheet FETs”, IEEE Transactions on Electron Devices, DOI: 10.1109/TED.2021.3130015, vol. 69, no. 1, pp. 380-387, Jan. 2022. |
en_US |
| dc.identifier.issn |
1557-9646 |
|
| dc.identifier.issn |
0018-9383 |
|
| dc.identifier.uri |
https://doi.org/10.1109/TED.2021.3130015 |
|
| dc.identifier.uri |
https://repository.iitgn.ac.in/handle/123456789/7355 |
|
| dc.description.abstract |
In this work, a physics-based compact model for channel charges and drain current in nanosheet FETs is presented. The model follows the bottom-up approach. The channel charges are calculated using the 1-D density of states (DOS), which seamlessly scales up for devices with 2-D or 3-D DOS as the confinement reduces in a particular direction. The model uses full Fermi-Dirac (FD) statistics and requires only two additional fitting parameters. The accuracy of the model is confirmed by comparing it with data from in-house 2-D coupled Poisson-Schr�dinger (PS) solver and Technology Computer Aided Tool (TCAD) simulations. The proposed model accurately predicts the subband energies, inversion charges, channel potential, and drain current for nanosheet FETs (NsFETs) with different dimensions and applied biases |
|
| dc.description.statementofresponsibility |
by Mohit D. Ganeriwala, Aishwarya Singh, Abhilash Dubey, Ramandeep Kaur and Nihar Ranjan Mohapatra |
|
| dc.format.extent |
vol. 69, no. 1, pp. 380-387 |
|
| dc.language.iso |
en_US |
en_US |
| dc.publisher |
Institute of Electrical and Electronics Engineers |
en_US |
| dc.subject |
Mathematical models |
en_US |
| dc.subject |
Computational modeling |
en_US |
| dc.subject |
Logic gates |
en_US |
| dc.subject |
Field effect transistors |
en_US |
| dc.subject |
Energy states |
en_US |
| dc.subject |
Semiconductor device modeling |
en_US |
| dc.subject |
Electric potential |
en_US |
| dc.title |
A bottom-up scalable compact model for quantum confined nanosheet FETs |
en_US |
| dc.type |
Article |
en_US |
| dc.relation.journal |
IEEE Transactions on Electron Devices |
|