Unified theory of the capacitance behavior in LDMOS devices

Abstract

This article reviews and provides physical insights into the anomalous capacitance behavior of laterally diffused MOS (LDMOS) transistors. It is shown that the modulation of channel/drift junction potential with VG , VD , and VS is primarily responsible for the capacitance peaks observed at different bias conditions. The VGS at which these capacitances peak and their magnitude depends on the channel doping gradient (CDG) and drift region parameters. Simple mathematical models valid across all bias regimes are proposed to explain the anomalous behavior. Different LDMOS device designs are also suggested to mitigate or delay the capacitance peaks