| dc.contributor.author |
Parmar, Alok |
|
| dc.contributor.author |
Prasad, Kailash |
|
| dc.contributor.author |
Rao, Nanditha |
|
| dc.contributor.author |
Mekie, Joycee |
|
| dc.contributor.other |
23rd International Symposium on Quality Electronic Design (ISQED 2022) |
|
| dc.coverage.spatial |
Santa Clara, US |
|
| dc.date.accessioned |
2022-07-28T12:48:52Z |
|
| dc.date.available |
2022-07-28T12:48:52Z |
|
| dc.date.issued |
06-04-22 |
|
| dc.identifier.citation |
Parmar, Alok; Prasad, Kailash; Rao, Nanditha and Mekie, Joycee, "FastMem: a fast architecture-aware memory layout design", in the 23rd International Symposium on Quality Electronic Design (ISQED 2022), Santa Clara, US, Apr. 6-7, 2022. |
en_US |
| dc.identifier.uri |
https://repository.iitgn.ac.in/handle/123456789/7936 |
|
| dc.description.statementofresponsibility |
by Alok Parmar, Kailash Prasad, Nanditha Rao and Joycee Mekie |
|
| dc.language.iso |
en_US |
en_US |
| dc.title |
FastMem: a fast architecture-aware memory layout design |
en_US |
| dc.type |
Conference Paper |
en_US |