Surrogate models for device design using sample-efficient deep learning

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dc.contributor.author Patel, Rutu
dc.contributor.author Mohapatra, Nihar Ranjan
dc.contributor.author Hegde, Ravi S.
dc.coverage.spatial United States of America
dc.date.accessioned 2022-11-30T15:56:20Z
dc.date.available 2022-11-30T15:56:20Z
dc.date.issued 2023-01
dc.identifier.citation Patel, Rutu; Mohapatra, Nihar Ranjan and Hegde, Ravi S., "Surrogate models for device design using sample-efficient deep learning", Solid-State Electronics, DOI: 10.1016/j.sse.2022.108505, vol. 199, Jan. 2023. en_US
dc.identifier.issn 0038-1101
dc.identifier.issn 1879-2405
dc.identifier.uri https://doi.org/10.1016/j.sse.2022.108505
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/8353
dc.description.abstract Generation of training dataset for machine learning-based device design algorithm is expensive. To address this, we propose an active learning approach. Its efficiency is demonstrated through a Deep Neural Network (DNN) based Laterally Diffused Metal Oxide Semiconductor Field-effect Transistor (LDMOSFET) off-state breakdown voltage (BVDS,off) and specific on-resistance (Rsp) predictor. Our results show the possibility of 50% reduction in the training dataset size without compromising the baseline accuracy. Specifically, we compared eight sampling techniques and found that Informative-Query by Committee (I-QBC) and Diverse Informative-Greedy Sampling (DI-GS) techniques work best with Euclidean Norm of Prediction Error (ENPE).
dc.description.statementofresponsibility by Rutu Patel, Nihar Ranjan Mohapatra and Ravi S. Hegde
dc.format.extent vol. 199
dc.language.iso en_US en_US
dc.publisher Elsevier en_US
dc.subject Deep neural networks en_US
dc.subject LDMOSFET en_US
dc.subject BVDS en_US
dc.subject DI-GS en_US
dc.subject ENPE en_US
dc.title Surrogate models for device design using sample-efficient deep learning en_US
dc.type Journal Paper en_US
dc.relation.journal Solid-State Electronics


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