Impact of optimal design point on performance metrics of DNN accelerators in FPGA

Show simple item record

dc.contributor.author Issac, Tom Glint
dc.contributor.author Gupta, Aryan
dc.contributor.author Giftson, Daniel
dc.contributor.author Shah, Gaurav
dc.contributor.author Patel, Vrajesh
dc.contributor.author Chudasama, Ruchit
dc.contributor.author More, Sukanya
dc.contributor.author Mekie, Joycee
dc.contributor.other IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2023)
dc.coverage.spatial United States of America
dc.date.accessioned 2023-07-28T15:18:23Z
dc.date.available 2023-07-28T15:18:23Z
dc.date.issued 4/23/2023
dc.identifier.citation Issac, Tom Glint; Gupta, Aryan; Giftson, Daniel; Shah, Gaurav; Patel, Vrajesh; Chudasama, Ruchit; More, Sukanya and Mekie, Joycee, "Impact of optimal design point on performance metrics of DNN accelerators in FPGA", in the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS 2023), Raleigh, US, Apr. 23-25, 2023.
dc.identifier.uri https://repository.iitgn.ac.in/handle/123456789/9062
dc.description.statementofresponsibility by Tom Glint Issac, Aryan Gupta, Daniel Giftson, Gaurav Shah, Vrajesh Patel, Ruchit Chudasama, Sukanya More and Joycee Mekie
dc.language.iso en_US
dc.title Impact of optimal design point on performance metrics of DNN accelerators in FPGA
dc.type Conference Paper


Files in this item

Files Size Format View

There are no files associated with this item.

This item appears in the following Collection(s)

Show simple item record

Search Digital Repository


Browse

My Account