Abstract:
In this study, we have evaluated the impact of sheet thickness scaling on the device performance of n-type nanosheet FETs (NsFETs) using k.p and Boltzmann transport equation (BTE) simulations. We have observed improved gate electrostatics, effective electron mobility, and device performance with scaling of the sheet thickness, which is primarily due to improvement in centroid capacitance and reduction in intervalley phonon scattering (IVS). Through extensive simulation and analysis, we have shown that a NsFET with 3 nm sheet thickness, zero silicon surface roughness, and 1GPa tensile channel stress can achieve the on-current target set by the IRDS 2023 edition. However, the contact resistance will play the spoilsport and the minimization of the contact resistance is necessary to maximize the benefits obtained from the sheet thickness scaling. The findings of this work shines some light on the feasibility of sheet thickness scaling for NsFET-based CMOS technology.