FP-BMAC: efficient approximate floating-point bit-parallel MAC processor using IMC

Abstract

In-memory computing (IMC) has emerged as a promising solution to address the energy and performance bottlenecks of traditional von Neumann architectures. This paper presents FP-BMAC, a novel bit-parallel in-memory computing architecture that efficiently handles floating-point multiply-and-accumulate (MAC) operations with reconfigurable FP precision. The architecture employs a novel approach to compute mantissa bits using an approximate right-shift multiplication method, which ensures alignment of output mantissa length with the input and enhances storage efficiency. The architecture effectively reduces computation delays and improves overall performance by incorporating BL Separator and BL Boosting circuits. The bit-parallel IMC macro achieves remarkable energy efficiency improvements, achieving a normalized throughput of 12.19 GFLOPS/Kb for FP Multiplication and 16.94 TFLOPS/W for MAC Operation at 1.15 GHz in CMOS 28nm technology.