SDR-PUF: sequence-dependent reconfigurable SRAM PUF with an exponential CRP space

Abstract

Approximate computing is a promising paradigm for improving the power efficiency of electronic systems for error-tolerant applications such as multimedia processing, image multiplication, and machine learning. In approximate computing, the accuracy of the computation is intentionally sacrificed to achieve lower power consumption and/or area. This study proposes a hybrid CMOS-memristor circuit design for approximate computing. The proposed design combines the advantages of CMOS technology, such as high scalability and flexibility, with the advantages of memristor technology, such as low power consumption and high density. The study first presents the design of fundamental logic gates using the hybrid CMOS-memristor approach. It then presents the design of six different 4-2 compressors with varying accuracy-performance tradeoffs. Finally, it presents the design of an 8x8 multiplier using the implemented compressors. The results show that using the hybrid CMOS-memristor circuit design achieves significant improvements in power efficiency over traditional CMOS designs. For example, the 8x8 multiplier design achieves up to 88% lower power consumption and uses up to 50% fewer transistors than a traditional CMOS design. The study also evaluated the proposed design for two neural network applications (LeNet5 and ResNetl8) and three image processing applications. The results show that the proposed design can achieve significant improvements in power efficiency for these applications as well.