Hybrid CMOS-memristor logic for boosting the power-efficiency in error tolerant applications

Abstract

Physical unclonable functions (PUFs) based on static random access memory (SRAM) are essential in security applications, generating unique challenge-response pairs (CRPs) from manufacturing randomness. These CRPs serve as a foundational element in cryptographic systems, ensuring device authenticity. Two major proposed SRAM PUFs are sequence-dependent and reconfigurable SRAM PUFs. Sequence-dependent SRAM PUFs produce a limited range of CRPs, while reconfigurable SRAM PUFs face a similar limitation, even though individual cells can have a considerable CRP space. The single cell in reconfigurable designs also adds to area consumption. Consequently, both types are classified as weak PUFs. To address these challenges, we introduce a novel approach, SDR-PUF, that combines sequence-dependence and reconfigurability in SRAM PUFs. This approach assigns a unique challenge to each column in the PUF array, diversifying the CRP space exponentially. Notably, the PUF design enhances security without a significant increase in area. We implemented an SDR-PUF array of size 8×8 in CMOS 28nm to assess our method’s efficacy. The results were promising: our design produced a vast number of unique CRPs, 9.12×1070, for a set of 32-bit challenges with a sequence length of 5. Furthermore, our design achieved a high throughput of 7.6Gbps at 0.9 V and consumes 0.14pJ energy per bit at 0.9 V for a sequence length of 5, showcasing its efficiency with a nominal native bit error rate and a high inter-hamming distance.