dc.contributor.author |
Sharma, Prateek |
|
dc.contributor.author |
Pal, Jaisingh |
|
dc.contributor.author |
Lashkare, Sandip |
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dc.contributor.other |
8th IEEE Electron Devices Technology and Manufacturing Conference (EDTM 2024) |
|
dc.coverage.spatial |
India |
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dc.date.accessioned |
2024-05-16T14:32:40Z |
|
dc.date.available |
2024-05-16T14:32:40Z |
|
dc.date.issued |
2024-03-03 |
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dc.identifier.citation |
Sharma, Prateek; Pal, Jaisingh and Lashkare, Sandip, "Bit-wise logical operations using capacitor-less silicon-on-insulator MOSFET for in-memory computing", in the 8th IEEE Electron Devices Technology and Manufacturing Conference (EDTM 2024), Bangalore, IN, Mar. 03-06, 2024. |
|
dc.identifier.uri |
https://doi.org/10.1109/EDTM58488.2024.10511766 |
|
dc.identifier.uri |
https://repository.iitgn.ac.in/handle/123456789/10056 |
|
dc.description.abstract |
In this paper, Silicon-on-Insulator (SOI) MOSFET for capacitor-less in-memory computing (IMC) is proposed to demonstrate logical operations. A methodology is presented using 3 SOI MOSFETs to realize AND/OR logic operations using one of the SOI MOSFETs as a selector between AND/OR operations. The band-to-band tunneling physics-based charge storage in a sub-threshold regime allows energy-efficient data storage. The proposed capacitor-less architecture along with the high energy-efficiency has the potential to realize large-scale implementation of hardware IMC. |
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dc.description.statementofresponsibility |
by Prateek Sharma, Jaisingh Pal and Sandip Lashkare |
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dc.language.iso |
en_US |
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dc.publisher |
Institute of Electrical and Electronics Engineers (IEEE) |
|
dc.subject |
SOI |
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dc.subject |
In-memory computing |
|
dc.subject |
Capacitor-less DRAM |
|
dc.subject |
Floating-body |
|
dc.title |
Bit-wise logical operations using capacitor-less silicon-on-insulator MOSFET for in-memory computing |
|
dc.type |
Conference Paper |
|