Abstract:
Large spiking neural networks (SNNs) require ultralow power and low variability hardware for neuromorphic computing applications. Recently, a band-to-band tunneling (BTBT)-based integrator was proposed, enabling the sub-kHz operation of neurons with area and energy efficiency. For an ultralow-power implementation of such neurons, a very low BTBT current is needed, so minimizing current without degrading neuronal properties is essential. Low variability is needed in the ultralow current integrator to avoid network performance degradation in a large BTBT neuron-based SNN. This work addresses device optimization to achieve low BTBT current. We conducted design space and variability analysis in technology computer-aided design (TCAD), utilizing a well-calibrated TCAD deck with experimental data from GlobalFoundries (GFs) 32 nm partially depleted silicon-on-insulator (PD-SOI) MOSFET. First, we discuss the physics-based explanation of the tunneling mechanism. Second, we explore the impact of device design parameters on SOI MOSFET performance, highlighting parameter sensitivities to tunneling current. With device parameters’ optimization, we demonstrate a $\sim$ 20 $\times$ reduction in BTBT current compared to the experimental data. Finally, a variability analysis that includes the effects of random dopant fluctuations (RDFs), oxide thickness variation (OTV), and channel–oxide interface traps ( D $_{\text{IT}}$ ) in the BTBT, subthreshold (SS), and ON regimes of operation is shown. The BTBT regime shows the highest sensitivity to OTV, with variability increasing by up to 25 $\times$ compared to the SS regime. In contrast, RDF and D $_{\text{IT}}$ variability resulted in a 1.25 $\times$ to $\sim$ 10 $\times$ lower coefficient of variation (CV) in the BTBT regime than in the SS regime, indicating better resilience to these sources of variability. The study provides essential design guidelines to enable energy-efficient neuromorphic computing, achieving biologically plausible sub-kHz spiking frequencies.