Investigating the analog performace of FinFETs in sub-10nm Wfin regime by analyzing the drain saturation voltage (VDS,SAT )

dc.contributor.advisor	Mohapatra, Nihar Ranjan
dc.contributor.author	Jain, Shubham
dc.date.accessioned	2020-12-03T09:26:01Z
dc.date.available	2020-12-03T09:26:01Z
dc.date.issued	2020
dc.identifier.citation	Jain, Shubham (2020). Investigating the analog performace of FinFETs in sub-10nm Wfin regime by analyzing the drain saturation voltage (VDS,SAT ). Gandhinagar: Indian Institute of Technology Gandhinagar, 51p. (Acc. No.: T00646).
dc.identifier.uri	https://repository.iitgn.ac.in/handle/123456789/6052
dc.description.statementofresponsibility	by Shubham Jain
dc.format.extent	vii, 51p.: ill.; 30 cm.
dc.language.iso	en_US
dc.publisher	Indian Institute of Technology Gandhinagar
dc.subject	18210080
dc.subject	Electrical Engineering
dc.subject	TCAD Simulation
dc.subject	RF parameters
dc.subject	Semiconductor Devices
dc.subject	CMOS Technology
dc.title	Investigating the analog performace of FinFETs in sub-10nm Wfin regime by analyzing the drain saturation voltage (VDS,SAT )
dc.type	Thesis
dc.contributor.department	Electrical Engineering
dc.description.degree	M.Tech.