Design and optimization of high voltage (HV) drain extended FinFET transistors for analog SoC applications

dc.contributor.advisor	Mohapatra, Nihar Ranjan
dc.contributor.author	Pal, Priyanjana
dc.date.accessioned	2020-12-03T09:26:02Z
dc.date.available	2020-12-03T09:26:02Z
dc.date.issued	2020
dc.identifier.citation	Pal, Priyanjana (2020). Design and optimization of high voltage (HV) drain extended FinFET transistors for analog SoC applications. Gandhinagar: Indian Institute of Technology Gandhinagar, 60p. (Acc. No.: T00660).
dc.identifier.uri	https://repository.iitgn.ac.in/handle/123456789/6066
dc.description.statementofresponsibility	by Priyanjana Pal
dc.format.extent	ix, 60p.: ill.; 30 cm.
dc.language.iso	en_US
dc.publisher	Indian Institute of Technology Gandhinagar
dc.subject	18250024
dc.subject	Electrical Engineering
dc.subject	Sub-micron CMOS Technology
dc.subject	Drain-extended FinFET (DeFinFET)
dc.subject	High Voltage Devices
dc.subject	Planar MOSFETs
dc.title	Design and optimization of high voltage (HV) drain extended FinFET transistors for analog SoC applications
dc.type	Thesis
dc.contributor.department	Electrical Engineering
dc.description.degree	M.Tech.